Every impedance change for a travelling wave along it's way will cause an reflected wave. The reflected voltage wave form, polarity and their wave currents depending on the impedance along the way. The measured voltage depends not only on time, also on location. Only a equal impedance won't change the waveform characterics, but the amplitude decreases along it's way to the receiving element.
Source Impedance = Transmission Line Impedance = Load Impedance
The basic mathematic equations are not difficult for travelling waves on a line, but to understand it in the reality is much more difficult.
|The bottom 5V signal comes out from
the Hex CMOS Inverter with an appr. 10 ohms series resistor directly on
the inverter output. The settling-time-instrument is connected with a
40cm RG-58CU 50 ohms cable to the 1Mohm/20pF input of a Tektronix 7A26 Vertical Amplifier with 200 MHz bandwidth in a 7904.
The reflected wave comes back from the oscilloscope causing a high
ringing with about 3 volts overshooting. The slew rate of the
rising edge is very fast with this capacitve load (cable+1Mohm/20pF)
and a medium speed 200 MHz 7A26. The wiper of the series resistor
potentiometer was almost in zero position (I haven't measure it). With
the wiper in zero position, the overshoot reaches almost 4 volts ! The
gated-settling-time trace measured with a second 7A26 amplifier
in it's 20 MHz position.
The top trace is the gated-settling-time window with 500µV/DIV on the settle node. This trace is displayed here for information only to observe if a series resistor adjustment will cause a changed waveform of the DAC amplifier, fortunately I could not see any changes in waveform.
The timing information between both traces is not correct, because both traces were triggered with two time-base Plug-In's 7B85 and 7B80. The 5V trace has been moved horizontal to the right side of the CRT to show better the rising edge.
|Same conditions as decribes above, but with an increased series resistors of some hundred ohms. This takes high frequency contents away and decrease slew rate. Such a waveform is dangerous, because the rising edge is very distorted. In the worthwile midrange of the slope there is a small flat "shoulder" area, triggering in this area would cause increased jitter and a fast logic device could even start with oscillations or ringing. The good thing in this experiment, the waveform of the gated-settling-time has not changed.|